Rapid thermal processing (RTP) is a well known process used in the fabrication of semiconductor integrated circuits when it is desired to quickly heat a wafer or other substrate to a relatively high temperature required for a thermally activated process and to thereafter quickly cool the wafer. RTP chambers typically include an array of high-intensity incandescent lamps, often tungsten halogen lamps, which together with reflector cavities around the lamps direct high-intensity infra-red, visible, and near-ultraviolet radiation toward the wafer. The lamps can be quickly turned on and off, and wafer temperatures in excess of 1000° C. can be achieved in times on the order of 10s or less. An example of such an RTP chamber is the Radiance RTP chamber available from Applied Materials, Inc. of Santa Clara, Calif.
Recently, RTP has been applied to the formation of Silicon-on-Insulator (SOI) wafers fabricated by the cleavage technique developed by SOITEC. In this process, as illustrated in the cross-sectional view of FIG. 1, energetic hydrogen ions H+ are implanted at a predetermined depth from the top surface of a silicon donor wafer 10 to form a hydrogen-rich layer 12. The top surface is then oxidized to form an oxide layer 14 of SiO2, as illustrated in the cross-sectional view of FIG. 2. The oxide layer 14 may have a thickness of about 150 nm, which consumes part of the silicon above the hydrogen-rich layer 12 leaving an underlying silicon layer 16. Exemplary thicknesses are 50 nm for the silicon layer 16 and 150 nm for the oxide layer 14 although the thickness may vary according to the eventual use of the SOI wafer. As illustrated in the cross-sectional view of FIG. 3, the donor wafer 10 is then inverted and bonded by a thermal process to a second, handle silicon wafer 20. Importantly for some aspects of the invention, present bonding techniques require the donor wafer 10 to be somewhat smaller than the handle wafer 20 so that a peripheral edge exclusion 22 develops at the top of the handle wafer 20 outside of the SOI stack. For a 300 mm SOI wafer, the edge exclusion 22 may be approximately 1 to 3 mm wide.
In one method of obtaining the SOI wafer, the hydrogen-rich layer 12 is stressed and chemical or mechanical techniques are used to cleave the bonded wafers 10, 20 along the cleavage line of the hydrogen-rich layer 12, leaving an SOI wafer 24 illustrated in the cross-sectional view of FIG. 4. The SOI wafer 24 includes the monocrystalline silicon layer 16 electrically isolated from the silicon handle wafer 20 by the insulating oxide layer 14. SOI wafers have many uses. Very advanced silicon integrated circuits can be formed in the silicon layer 16 with virtually no leakage or parasitic capacitance to or through the silicon substrate 20, thereby lowering the power consumption and increasing the processing speed of the integrated circuit form in the isolated silicon layer 16. SOI wafers have other uses including micro electromechanical system (MEMS) wafers in which electrically actuated micro structures are formed in silicon layers.
However, the cleavage process does not leave a smooth upper surface in the silicon layer 16. Instead, as illustrated in the expanded cross-sectional view of FIG. 5, an upper surface 26 of the silicon layer 16 is very rough, exhibiting peaks and valleys. It has been found that an RTP anneal in an ambient of argon and hydrogen gases for 30s at 1200° C. is effective at smoothing the structure to form a smooth upper surface 28, illustrated in FIG. 6.
There are other methods of obtaining SOI wafers by layer cleaving, some of which are described by Wolf in Silicon Processing for the VLSI Era, vol. 4: Deep-Submicron Process Technology, Lattice Press, 2002, pp. 527-550. Any layer having a cleaved surface is expected to show roughness that needs to be smoothed.
An RTP chamber is well suited for the required smoothing anneal. However, it has become apparent that the temperature must be closely controlled across the wafer. Variations in temperature of as little as 1° C. can cause a defect known as crystal slip, a crystallographic line defect that may extend for distances that may be visible. The slip defect is equivalent to a stress-induced fracture of the monocrystalline silicon layer 16. Any chip containing a slip defect is either inoperative or subject to early failure. The Radiance RTP chamber includes pyrometry and temperature control based on separate control of multiple, for example, seven annular heating zones. The temperature control should be able to provide the required temperature uniformity of 1° C. at 1200° C. Nonetheless, SOI wafers have continued to exhibit unacceptable number of slip defects.
Neyret et al. in U.S. Pat. No. 6,853,802 have suggested that the slip problem arises from the edge exclusion 22. Their solution is to include an extra ring around the wafer periphery to adjust the thermal control at the wafer edge exclusion 22. This solution however is felt to be inflexible since the extra ring needs to be optimized for the different combinations of silicon and oxide thicknesses.